【2】Verilog练习-补码转化与7段译码逻辑设计

补码转化

程序

//补码转化逻辑
`timescale 1ns/10ps
module comp_conv(
                a,
                a_comp
                );
input[7:0]        a;
output[7:0]        a_comp;
//wire[6:0]        b;//按位取反的幅度位
//wire[7:0]        y;//负数的补码；
//assign            b=~a[6:0];
//assign            y[6:0]=b+1;//按位取反+1
//assign            y[6:0]=~a[6:0]+1;//按位取反+1
//assign            y[7]=a[7];//符号位不变 
//assign            y={a[7],~a[6:0]+1};
//assign            a_comp=a[7]?y:a;//二选一
assign            a_comp=a[7]?{a[7],~a[6:0]+1}:a;//二选一
endmodule
//----testbench of comp_conv---
module comp_conv_tb;
reg[7:0]            a_in;
wire[7:0]            y_out;
comp_conv comp_conv(
                    .a(a_in),
                    .a_comp(y_out)
                    );
initial begin
                    a_in<=0;
            #3000    $stop;
end
always #10 a_in<=a_in+1;
endmodule

现象

7段译码逻辑设计

代码：

//七段码译码器
`timescale 1ns/10ps
module seg_dec(
                    num,
                    a_g
                    );
input[3:0]            num;
output[6:0]            a_g;//a_g-->{a,b,c,d,e,f,g}
reg[6:0]            a_g;
always@(num)begin
  case(num)
  4'd0: begin a_g<=7'b111_1110; end
  4'd1: begin a_g<=7'b011_0000; end 
  4'd2: begin a_g<=7'b110_1101; end
  4'd3: begin a_g<=7'b111_1100; end
  4'd4: begin a_g<=7'b011_0011; end
  4'd5: begin a_g<=7'b101_1011; end
  4'd6: begin a_g<=7'b101_1111; end
  4'd7: begin a_g<=7'b111_0000; end
  4'd8: begin a_g<=7'b111_1111; end
  4'd9: begin a_g<=7'b111_1011; end
  default: begin a_g<=7'b000_0001; end//中杠  
  endcase
end
endmodule
//----testbench of seg_dec---
module seg_dec_tb;
reg[3:0]            num_in;
wire[6:0]            a_g_out;
seg_dec seg_dec(
                    .num(num_in),
                    .a_g(a_g_out)
                    );
initial begin
                    num_in<=0;
            #200    $stop;
end
always #10 num_in<=num_in+1;
                    
endmodule

现象