【6】Verilog练习-三角波梯形波发生器

三角波发生器理论

代码

//三角波发生器
`timescale 1ns/10ps
module tri_gen(
                clk,
                res,
                d_out
                );
input            clk;
input            res;
output[8:0]        d_out;
reg                state;
reg[8:0]        d_out;
always@(posedge clk or negedge res)
if(~res) begin
    state<=0;d_out<=0;
end
else begin
                case(state)
                0://上升
                begin
                  d_out<=d_out+1;
                  if(d_out==299)begin
                   state<=1;
                  end
                end
                1://下降
                begin
                  d_out<=d_out-1;
                  if(d_out==1)begin
                    state<=0;
                  end
                end
                endcase
end
endmodule
//------testbench of tri_gen----
module tri_gen_tb;
reg                clk,res;
wire[8:0]        d_out;
tri_gen U1(
                .clk(clk),
                .res(res),
                .d_out(d_out)
                );
initial begin
                clk<=0;res<=0;
        #17        res<=1;
        #8000    $stop;
end
always #5 clk<=~clk;
endmodule

现象

梯形波发生器

//三角波发生器->改进为梯形波
`timescale 1ns/10ps
module tri_gen(
                clk,
                res,
                d_out
                );
input            clk;
input            res;
output[8:0]        d_out;
reg[1:0]        state;//3个状态2位，不在是原来的1bit
reg[8:0]        d_out;
reg[7:0]        con;//计数器，记录平顶周期个数
always@(posedge clk or negedge res)
if(~res) begin
    state<=0;d_out<=0;con<=0;
end
else begin
                case(state)
                0://上升
                begin
                  d_out<=d_out+1;
                  if(d_out==299)begin
                   state<=1;
                  end
                end
                1://平顶
                begin
                  if(con==200) begin
                    state<=2;
                    con<=0;
                  end
                  else begin
                     con<=con+1;
                  end
                end
                2://下降
                begin
                  d_out<=d_out-1;
                  if(d_out==1)begin
                    state<=0;
                  end
                end
                default://3状态
                begin
                  state<=0;
                  con<=0;
                end
                endcase
end
endmodule
//------testbench of tri_gen----
module tri_gen_tb;
reg                clk,res;
wire[8:0]        d_out;
tri_gen U1(
                .clk(clk),
                .res(res),
                .d_out(d_out)
                );
initial begin
                clk<=0;res<=0;
        #17        res<=1;
        #20000    $stop;
end
always #5 clk<=~clk;
endmodule

现象