VHDL语言38译码器

元件查看端口方法Tool>>Netlist Viewers>>RTL Viewers

library ieee;
use ieee.std_logic_1164.all;
entity decoder38 is
port (a,b,c,g1,g2,g3:in std_logic;
      y:out std_logic_vector(7 downto 0));
end decoder38;
architecture rtl of decoder38 is
signal cba: std_logic_vector(2 downto 0);
begin
 cba<=c&b&a;
process(cba,g1,g2,g3)
begin
if (g1='1' and g2='0' and g3='0') then
case cba is
when "000"=>y<="11111110";
when "001"=>y<="11111101";
when "010"=>y<="11111011"; 
when "011"=>y<="11110111" ;
when "100"=>y<="11101111" ;
when "101"=>y<="11011111" ; 
when "110"=>y<="10111111" ;
when "111"=>y<="01111111";
when  others=>y<="XXXXXXXX";
end case;
else
y<="11111111";
end if;
end process;
end rtl;