【2】Verilog练习-组合逻辑电路多路选择器

二选一逻辑设计

程序

//二选一逻辑设计
`timescale 1ns/10ps
module fn_sw(
            a,
            b,
            sel,
            y
            );
input        a;
input        b;
input        sel;
output        y;

//assign        y=sel?(a^b):(a&b);
//用always语句块实现组合逻辑；
reg            y;

always@(a or b or sel)
    if(sel==1)begin
        y<=a^b;
    end
    else begin
        y<=a&b;
    end
endmodule

//---testbench of fn_sw----
module fn_sw_tb;
reg            a,b,sel;//输入reg型
wire        y;//输出wire型
fn_sw fn_sw(
            .a(a),
            .b(b),
            .sel(sel),
            .y(y)
            );
initial begin
            a<=0;b<=0;sel<=0;
        #10 a<=0;b<=0;sel<=1;
        #10 a<=0;b<=1;sel<=0;
        #10 a<=1;b<=0;sel<=0;
        #10 a<=1;b<=0;sel<=1;
        #10 a<=1;b<=1;sel<=0;
        #10 a<=1;b<=1;sel<=1;
        #10 $stop;
end
endmodule

现象

多路选择逻辑设计

代码

//四选一逻辑设计
`timescale 1ns/10ps
module fn_sw_4(
                a,
                b,
                sel,
                y
                );

input            a;
input            b;
input[1:0]        sel;
output            y;
reg                y;
always@(a or b or sel)begin

    case(sel)
    2'b00:begin y<=a&b;end
    2'b01:begin y<=a|b;end
    2'b10:begin y<=a^b;end
    2'b11:begin y<=~(a^b);end
    endcase

end
endmodule
//-----testbench of fn_sw_4--
module fn_sw_4_tb;
reg[3:0]            absel;
wire                y;
fn_sw_4 fn_sw_4(
                .a(absel[0]),
                .b(absel[1]),
                .sel(absel[3:2]),
                .y(y)
                );
initial begin
                absel<=0;
                #300 $stop;
end

always #10 absel<=absel+1; 

endmodule

现象